1. Field of the Invention
The present invention relates to a system power supply apparatus that includes a plurality of circuits for providing constant voltages, and in particular, to a system power supply apparatus capable of controlling output voltages outputted from the plurality of constant voltage circuits when the system power supply apparatus starts up.
2. Discussion of the Background Art
Recently, as an electronic instrument increases a number of functions, a specification of a power supply becomes complex. For example, a plurality of voltages are generally demanded in one instrument, and accordingly, a relation between rising voltages is ruled. Then, a conventional microcomputer use power supply includes an A/D converter and necessitates a high precision power supply voltage to generate a reference power supply voltage Vref of the A/D converter beside a main power supply voltage Vdd as discussed in Japanese Patent Application Laid Open No. 2001-142548.
Further, the reference power supply voltage Vref needs to be controlled not to exceed the main power supply voltage Vdd to avoid latch up of the microcomputer at least when the power supply is turned on and off.
The power supply circuit generates the main power supply voltage Vdd of the microcomputer, and includes a DC-DC converter. A circuit generating the reference power supply voltage Vref employs an analog regulator 101 as shown in FIG. 6. Since an output voltage of the DC-DC converter generally slowly rises than the analog regulator, the reference power supply Vref rises faster than the main power supply voltage Vdd when the power supply is turned on without any counter measures there against. Thus, the reference voltage Vref becomes larger than the main power supply voltage Vdd.
Then, in the past, a control circuit 102 is added as shown in FIG. 6. Specifically, a resistance Rc and a constant current source ia are serially connected between the reference voltage Vref, outputted from the analog regulator 101, and ground so as to compare a voltage Va, smaller than the reference power supply voltage Vref by a voltage decreased by the resistance Rc, with the main power supply voltage Vdd in the control circuit 102. An operational amplifier circuit AMPb controls a transistor Tc connected to a base of a transistor Tb so that the voltage Va is controlled to become the main power supply voltage Vdd. Thus, the reference voltage Vref rises to a voltage smaller than that of the main power supply voltage Vdd along with rise of the main power supply voltage Vdd when the power supply is turned on.
However, when a difference in voltage between the Vdd and the Vref during their rising is ruled in addition to an order of reaching respective target voltages after a power supply is turned on, a circuit of FIG. 6 sometimes can't follow such a rule. For example, it is true when first and second power supply voltages rise quickly and slowly, respectively, and the first power supply voltage should reach the target voltage earlier that the second's, and a difference between the first and second voltages should be controlled not to exceed a prescribed value. Specifically, if the second power supply voltage rises too slowly, the difference exceeds the value, thereby dissatisfying a prescribed specification.
When the same type circuits, such as analog regulators, etc., constitute these power supply circuits, it is unknown that which of the respective output voltages outputted from these power supply circuits rises at a faster speed. Further, a rise time of an output voltage outputted from a power supply circuit largely depends on a load or a capacity of a bypath condenser connected to an output terminal of the power supply circuit. As a result, an order of a rise time of the output voltages outputted from these power supply circuits sometimes varies depending on a condition of the load or capacity.
FIGS. 7 to 9 illustrate various rising examples of output voltages VoA and VoB in the first and second constant voltage circuits, wherein VoA represents an output voltage of the first constant voltage circuit, whereas VoB, the second constant voltage circuit, respectively. Delta V represents a voltage difference between the respective output voltages VoA and VoB (i.e., VoA −VoB) VA and VB are target voltages of the output voltages VoA and VoB, respectively. Further, tA and tB are times when the output voltages VoA and VoB reach the target voltages VA and VB, respectively.
Now, it is herein below supposed that the below described first and second inequalities are given as rising conditions of the output voltages VoA and VoB, wherein Vc is a prescribed constant less than the target voltage VA;tA<tB(Hereinafter referred to as a first condition)Δ(delta)<Vc(Hereinafter referred to as a second condition)
FIG. 7 illustrates an example when these voltages VoA and VoB rise substantially the same speed. To meet the first condition, a sleep state of the first constant voltage circuit is released at the point A, and that of the second constant voltage circuit is released at the point B with a slight delay. As a result, the output voltages VoA and VoB rise substantially in parallel, and a voltage difference delta V is smaller than Vc as indicated by a two dotted line arrow. Thus, the below described condition is satisfied:tA<tB
However, when the output voltage VoB of the second constant voltage circuit rises with a delay even though the sleep statuses of the first and second constant voltage circuits are released at substantially the same time as shown in FIG. 8, Δ (delta) V exceeds Vc during the rising of those, and thereby dissatisfying the second condition.
Further, as shown in FIG. 9, one of when the output voltage VoB rises earlier, the output voltage VoA rises later, and the output voltage VoB rises earlier while the output voltage VoA rises later, the above-mentioned first condition can't be met even if the second condition can be met.